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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9774 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 14-bit, 32 msps txdac+? with 4 3 interpolation filters functional block diagram vco in/ext pll divide pllcom reflo pll clock multiplier refio snooze iouta fsadj ad9774 sleep dcom dvdd icomp acom avdd +1.2v reference and control amp pll enable plllock clk4 3 in pllvdd lpf ioutb edge triggered latches 14 14-bit dac data inputs (db13-db0) 2 3 2 3 1 3 2 3 4 3 4 3 14 14 14 clk in/out refcomp product description the ad9774 is a single supply, oversampling, 14-bit digital-to- analog converter (dac) optimized for waveform reconstruction applications requiring exceptional dynamic range. manufac- tured on an advanced cmos process, it integrates a complete, low distortion 14-bit dac with a 4 digital interpolation filter and clock multiplier. the two-stage, 4 digital interpolation filter provides more than a six-fold reduction in the complexity of the analog reconstruction-filter. it does so by multiplying the input data rate by a factor of four while simultaneously suppressing the original inband images by more than 69 db. the on-chip clock multiplier provides all the necessary clocks. the ad9774 can reconstruct full-scale waveforms having bandwidths as high as 13.5 mhz when operating at an input data rate of 32 msps and a dac output rate of 128 msps. the 14-bit dac provides differential current outputs to support differential or single-ended applications. a segmented current source architecture is combined with a proprietary switching tech- nique to reduce spurious components and enhance dynamic per- formance. matching between the two current outputs ensures enhanced dynamic performance in a differential output configura- tion. the differential current outputs may be fed into a transformer or tied directly to an output resistor to provide two complementary, single-ended voltage outputs. a differential op amp topology can also be used to obtain a single-ended output voltage. the output voltage compliance range is nominally 1.25 v. edge-triggered input latches, a 4 clock multiplier, and a tem- perature compensated bandgap reference have also been inte- grated to provide a complete monolithic dac solution. flexible supply options support +3 v and +5 v cmos logic families. ttl logic levels can also be accommodated by reducing the ad9774 digital supply. the on-chip reference and control amplifier are configured for maximum accuracy and flexibility. the ad9774 can be driven by the on-chip reference or by a variety of external reference voltages. the full-scale current of the ad9774 can be adjusted over a 2 ma to 20 ma range, thus providing additional gain ranging capabilities. the ad9774 is available in a 44-lead mqfp package. it is specified for operation over the industrial temperature range. product highlights 1. on-chip 4 interpolation filter eases analog reconstruction filter requirements by suppressing the first three images by 69 db. 2. low glitch and fast settling time provide outstanding dynamic performance for waveform reconstruction or digital synthesis requirements, including communications. 3. on-chip, edge-triggered input cmos latches interface readily to cmos and ttl logic families. the ad9774 can support input data rates up to 32 msps. 4. a temperature compensated, 1.20 v bandgap reference is included on-chip, providing a complete dac solution. an external reference may also be used. 5. the current output(s) of the ad9774 can easily be configured for various single-ended or differential circuit topologies. 6. on-chip clock multiplier generates all the high-speed clocks required by the internal interpolation filters. both 2 and 4 clocks are generated from the lower rate data clock supplied by the user. txdac+ is a trademark of analog devices, inc. features single 3 v or 5 v supply 14-bit dac resolution and input data width 32 msps input data rate at 5 v 13.5 mhz reconstruction bandwidth 12 enobs @ 1 mhz 77 dbc sfdr @ 5 mhz 4 3 interpolation filter 69 db image rejection 84% passband to nyquist ratio 0.002 db passband ripple 23 3/4 cycle latency internal 4 3 clock multiplier on-chip 1.20 v reference 44-lead mqfp package applications communication transmit channel: wireless basestations adsl/hfc modems direct digital synthesis (dds)
C2C rev. b ad9774Cspecifications dc specifications parameter min typ max units resolution 14 bits dc accuracy 1 integral linearity error (inl) t a = +25 c 4 lsb t min to t max differential nonlinearity (dnl) t a = +25 c 3 lsb t min to t max monotonicity (12-bit) guaranteed over rated specification temperature range analog output offset error C0.025 +0.025 % of fsr gain error (without internal reference) C7 1 +7 % of fsr gain error (with internal reference) +7.5 1 +7.5 % of fsr full-scale output current 2 20 ma output compliance range 1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 1 m a reference input input compliance range 0.1 1.25 v reference input resistance 1 m w temperature coefficients unipolar offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 100 ppm of fsr/ c power supply avdd voltage range 4 2.7 5.0 5.5 v analog supply current (i avdd ) 26.5 32 ma analog supply current in sleep mode (i avdd ) 3.2 5 ma pllvdd voltage range 2.7 5.0 5.5 v clock multiplier supply current (i pllvdd )1317ma dvdd voltage range 2.7 5.0 5.5 v digital supply current at 5 v (i dvdd ) 5 123.0 140.0 ma digital supply current at 5 v in snooze mode (i dvdd ) 42.0 50.0 ma digital supply current at 3 v (i dvdd ) 5 62.0 ma nominal power dissipation avdd and dvdd at 3 v 6 415 mw avdd and dvdd at 5 v 6 1125 mw power supply rejection ratio (psrr) 7 C avdd C0.2 +0.2 % of fsr/v power supply rejection ratio (psrr) 7 C pllvdd C0.025 +0.025 % of fsr/v power supply rejection ratio (psrr) 7 C dvdd C0.025 +0.025 % of fsr/v operating range C40 +85 c notes 1 measured at iouta driving a virtual ground. 2 nominal full-scale current, ioutfs, is 32 the i ref current. 3 use an external amplifier to drive any external load. 4 for operation below 3 v, it is recommended that the output current be reduced to 12 ma or less to maintain optimum performance. 5 measured at f clock = 25 msps and f out = 1.01 mhz. 6 measured as unbuffered voltage output into 50 w r load at iouta and ioutb, f clock = 32 msps and f out = 12.8 mhz. 7 5% power supply variation. specifications subject to change without notice. (t min to t max , avdd = +5 v, pllvdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted)
C3C rev. b ad9774 dynamic specifications parameter min typ max units dynamic performance maximum output update rate w/dvdd = 5 v 128 msps maximum output update rate w/dvdd = 3 v 100 128 msps output settling time (t st ) (to 0.025%) 35 ns output propagation delay (t pd ) 55 clocks 1 glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ ? hz 2 ac linearity to nyquist spurious-free dynamic range (sfdr) to nyquist f clock = 25 msps; f out = 1.01 mhz 0 dbfs output 79 db C6 dbfs output 86 db C12 dbfs output 75 db C18 dbfs output 75 db f clock = 32 msps; f out = 1.01 mhz 78 db f clock = 32 msps; f out = 5.01 mhz 77 db f clock = 32 msps; f out = 10.01 mhz 79 db f clock = 32 msps; f out = 13.01 mhz 78 db total harmonic distortion (thd) f clock = 25 msps; f out = 1.01 mhz; 0 dbfs C75 db signal-to-noise ratio (snr) f clock = 25 msps; f out = 1.01 mhz; 0 dbfs 76 db notes 1 propagation delay is delay from data input to dac update. 2 measured single-ended into 50 w load. specifications subject to change without notice. (t min to t max , avdd = +5 v, pllvdd = +5 v, dvdd = +5 v, i outfs = 20 ma, differential transformer coupled output, 50 v doubly terminated, unless otherwise noted) digital specifications parameter min typ max units digital inputs logic 1 voltage @ dvdd = +5 v 3.5 5 v logic 1 voltage @ dvdd = +3 v 2.1 3 v logic 0 voltage @ dvdd = +5 v 0 1.3 v logic 0 voltage @ dvdd = +3 v 0 0.9 v logic 1 current C10 +10 m a logic 0 current C10 +10 m a input capacitance 5 pf input setup time (t s ) 2.5 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw )4ns (t min to t max , avdd = +5 v, pllvdd = +5 v, dvdd = +5 v, i outfs = 20 ma unless otherwise noted) 0.025% 0.025% t s t h t lpw t pd t st db0Cdb11 clock iouta or ioutb figure 1. timing diagram
C4C rev. b ad9774Cspecifications digital filter specifications parameter min typ max units maximum input clock rate (f clock ) dvdd = 5 v 32 msps dvdd = 3 v 25 32 msps digital filter characteristics passband width 1 : 0.005 db 0.410 f out /f clock passband width: 0.01 db 0.414 f out /f clock passband width: 0.1 db 0.420 f out /f clock passband width: C3 db 0.482 f out /f clock linear phase (fir implementation) stopband rejection 0.591 f clock to 3.419 f clock C69.5 db 0.591 f clock to 1.409 f clock C79.5 db group delay 2 38 input clocks impulse response duration C40 db 53 input clocks C60 db 62 input clocks notes 1 excludes sinx/x characteristic of dac. 2 defined as the number of data clock cycles between impulse input and peak of output response. specifications subject to change without notice. (t min to t max , avdd = +2.7 v to +5.5 v, dvdd = +2.7 v to +5.5 v, i outfs = 20 ma unless otherwise noted) absolute maximum ratings* with respect parameter to min max units avdd acom C0.3 +6.5 v dvdd dcom C0.3 +6.5 v pllvdd pllcom C0.3 +6.5 v acom dcom C0.3 +0.3 v pllcom acom C0.3 +0.3 v pllcom dcom C0.3 +0.3 v avdd dvdd C6.5 +6.5 v pllvdd dvdd C0.3 +6.5 v pllvdd avdd C0.3 +6.5 v clkin, clk4 in dvdd C0.3 +6.5 v sleep, snooze dcom C0.3 dvdd + 0.3 v digital inputs dcom C0.3 dvdd + 0.3 v pll divide, lpf acom C0.3 pllvdd + 0.3 v plllock acom C0.3 pllvdd + 0.3 v vco in/ext acom C0.3 pllvdd + 0.3 v iouta/ioutb acom C0.3 avdd + 0.3 v refio, fsadj acom C0.3 avdd + 0.3 v fsadj acom C0.3 avdd + 0.3 v icomp acom C0.3 avdd + 0.3 v refcom acom C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature +300 c (10 sec) *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. ordering guide temperature package package model range description option* AD9774AS C40 c to +85 c 44-lead mqfp s-44 ad9774eb evaluation board *s = metric quad flatpack. thermal characteristic thermal resistance 44-lead mqfp q ja = 53.2 c/w q jc = 19 c/w
ad9774 C5C rev. b caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9774 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table i. integer filter coefficients for first stage interpola- tion filter (55-tap halfband fir filter) lower upper integer coefficient coefficient value h(1) h(55) C1 h(2) h(54) 0 h(3) h(53) 3 h(4) h(52) 0 h(5) h(51) C7 h(6) h(50) 0 h(7) h(49) 15 h(8) h(48) 0 h(9) h(47) C28 h(10) h(46) 0 h(11) h(45) 49 h(12) h(44) 0 h(13) h(43) C81 h(14) h(42) 0 h(15) h(41) 128 h(16) h(40) 0 h(17) h(39) C196 h(18) h(38) 0 h(19) h(37) 295 h(20) h(36) 0 h(21) h(35) C447 h(22) h(34) 0 h(23) h(33) 706 h(24) h(32) 0 h(25) h(31) C1274 h(26) h(30) 0 h(27) h(29) 3976 h(28) 6276 table ii. integer filter coefficients for second stage inter- polation filter (23-tap halfband fir filter) lower upper integer coefficient coefficient value h(1) h(23) C6 h(2) h(22) 0 h(3) h(21) 37 h(4) h(20) 0 h(5) h(19) C125 h(6) h(18) 0 h(7) h(17) 316 h(8) h(16) 0 h(9) h(15) C736 h(10) h(14) 0 h(11) h(13) 2562 h(12) 4096 frequency C dc to 2 3 f clock 0 C20 C180 0 0.5 output C dbfs C80 C120 C140 C160 C40 C60 C100 1.0 1.5 2.0 figure 2a. fir filter frequency response time C sam p les 1.0 C0.4 0 80 10 normalized output 20 30 40 50 60 70 0.8 0.4 0.2 0.0 C0.2 0.6 figure 2b. fir filter impulse response warning! esd sensitive device
ad9774 C6C rev. b pin function descriptions pin no. name description 1, 19, 40, 44 dcom digital common. 2 db13 most significant data bit (msb). 3C14 db12Cdb1 data bits 1C12. 15 db0 least significant data bit (lsb). 16, 17, 42 nc no internal connection. 18, 41 dvdd digital supply voltage (+2.7 v to +5.5 v). 20 clk in/out clock input when pll clock multiplier enabled. clock output when pll clock multiplier disabled. data latched on rising edge. 21 plllock phase lock loop lock signal. active high indicates pll is locked to input clock. 22 clk4 in external 4 clock input when pll is disabled. no connect when internal pll is active. 23 plldivide pll range control pin. connect to pllcom if clkin is above 10 msps. connect to pllvdd if clkin is between 10 msps and 5.5 msps. 24 vco in/ext internal voltage controlled oscillator (vco) enable/ disable pin. connect to pllvdd to en able vco. connect to pllcom to disable vco and drive clk4 in with external vco output. 25 lpf pll loop filter node. connect to externa l vco control input if internal vco disabled. 26 pllvdd p hase lock loop (pll) supply voltage (+2.7 v to +5.5 v). must be set to similar voltage as dvdd. 27 pllcom phase lock loop common. 28 pllenable phase lock loop enable. connect to pllvdd to enable. connect to pllcom to disable. 29 unused factory test. leave open. 30 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 31 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to acom). requires 0.1 m f capacitor to acom when internal reference activated. 32 fsadj full-scale current output adjust. 33 refcomp noise reduction node. add 0.1 m f to avdd. 34 acom analog common. 35 avdd analog supply voltage (+2.7 v to +5.5 v). 36 ioutb complementary dac current output. full-scale current when all data bits are 0s. 37 iouta dac current output. full-scale current when all data bits are 1s. 38 icomp internal bias node for switch driver circuitry. decouple to acom with 0.1 m f capacitor. 39 sleep power-down control input. active high. connect to dcom if not used. 43 snooze snooze control input. deactivates 4 interpolation filter to reduce digital power consumption only. active high. connect to dcom if not used. pin configuration 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 refcomp fsadj refio reflo unused pllenable pllcom ad9774 dcom db13 db12 db11 db10 db9 db8 nc = no connect db7 db6 db5 db4 pllvdd lpf vco in/ext plldivide db3 db2 db1 db0 nc nc dvdd dcom clk in/out plllock clk4 3 in ioutb acom dcom snooze dvdd iouta avdd dcom sleep icomp nc
ad9774 C7C rev. b definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (+25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree c. for reference drift, the drift is re- ported in ppm per degree c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). signal-to-noise ratio (snr) s/n is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. passband frequency band in which any input applied therein passes unattenuated to the dac output. stopband rejection the amount of attenuation of a frequency outside the passband applied to the dac, relative to a full-scale signal applied at the dac input within the passband. group delay number of input clocks between an impulse applied at the device input and peak dac output current. impulse response response of the device to an impulse applied to the input. vco in/ext pll divide pllcom reflo pll clock multiplier refio clk in/out snooze iouta fsadj ad9774 sleep dcom dvdd icomp acom avdd +1.2v reference and control amp pll enable plllock clk4 3 in pllvdd lpf ioutb edge triggered latches 14-bit dac 2 3 2 3 1 3 2 3 4 3 4 3 14 14 14 14 digital data tektronix awg-2021 50 v 20pf 50 v 20pf 0.1 m f 100 v mini-circuits t1-1t to hp3589a spectrum / network analyzer 50 v input 0.01 m f 1.5k v +3v d +3v d +3v d 0.1 m f +5v a 1.91k v 0.1 m f refcomp option 4 figure 3. basic ac characterization test setup
10db C div 10 C60 C90 0 128.0 25.6 51.2 76.8 102.4 0 C50 C70 C80 C30 C40 C10 C20 inband mhz figure 4. single tone spectral plot @ 32 msps w/f out = 12.8 mhz (dc to 4 clkin) 10db C div 10 C60 C90 0 64.0 12.8 25.6 38.4 51.2 C70 C80 0 C50 C30 C40 C10 C20 inband mhz figure 7. single tone spectral plot @ 16 msps w/f out = 6.4 mhz (dc to 4 clkin) 10db C div 10 C60 C90 0 32.0 6.4 12.8 19.2 25.6 0 C50 C70 C80 C30 C40 C10 C20 mhz figure 10. single tone spectral plot f out @ 8 msps w/f out = 3.2 mhz (dc to 4 clkin) ad9774 C8C rev. b typical ac characterization curves (avdd = +5 v, pllvdd = +3 v, dvdd = +3 v, i outfs = 20 ma, 50 v doubly terminated load, differential output, t a = +25 8 c, unless otherwise noted. note: pllvdd = +5 v and dvdd = +5 v for figures 4, 5 and 6.) f out C mhz sfdr C dbc 90 60 02 14 4681012 85 80 75 70 65 0dbfs C6dbfs C18dbfs C12dbfs figure 5. inband sfdr vs. f out @ 32 msps (dc to clkin/2) f out C mhz sfdr C dbc 90 60 0 17 23456 85 80 75 70 65 0dbfs C6dbfs C12dbfs C18dbfs figure 8. inband sfdr vs. f out @ 16 msps (dc to clkin/2) f out C mhz sfdr C dbc 90 60 0 0.5 3.5 1 1.5 2 2.5 3 85 80 75 70 65 0dbfs C6dbfs C12dbfs C18dbfs figure 11. inband sfdr vs. f out @ 8 msps (dc to clkin/2) f out C mhz sfdr C dbc 85 35 0 214 4 6 8 10 12 80 55 50 45 40 70 60 75 65 0dbfs C6dbfs C12dbfs C18dbfs figure 6. out-of-band sfdr vs. f out @ 32 msps (clkin/2 to 3 1/2 clkin) f out C mhz sfdr C dbc 85 35 0 17 23456 80 55 50 45 40 70 60 75 65 0dbfs C6dbfs C12dbfs C18dbfs figure 9. out-of-band sfdr vs. f out @ 16 msps (clkin/2 to 3 1/2 clkin) f out C mhz sfdr C dbc 85 35 0 0.5 3.5 1 1.5 2 2.5 3 80 55 50 45 40 70 60 75 65 0dbfs C6dbfs C12dbfs C18dbfs figure 12. out-of-band sfdr vs. f out @ 8 msps (clkin/2 to 3 1/2 clkin)
ad9774 C9C rev. b 10db C div 10 C90 0 1.0 8.0 2.0 3.0 4.0 5.0 6.0 7.0 0 C30 C40 C60 C80 C10 C20 C50 C70 mhz figure 13. single tone spectral plot @ 2 msps w/f out = 800 khz (dc to 4 clkin) a in C dbfs sfdr C dbc 90 60 C18 C16 0 C14 C12 C10 C6 C4 C2 C8 85 80 75 70 65 1.45mhz @ 16msps 363khz @ 4msps 727khz @ 8msps 2.9mhz @ 32msps figure 16. in-band single tone sfdr vs. a in @ f out = f clock /7 (dc to clkin/2) a out C dbfs sfdr C dbc 80 50 C18 C16 0 C14 C12 C10 C6 C4 C2 C8 75 70 65 60 55 5.6/6.4mhz @ 16msps 1.4/1.6mhz @ 4msps 2.8/3.2mhz @ 8msps 11.2/12.8mhz @ 32msps figure 19. in-band two tone sfdr vs. a out @ f out = f clock /2.7 (dc to clkin/2) f out C mhz sfdr C dbc 90 60 0.1 0.2 0.8 0.3 0.4 0.5 0.6 0.7 85 80 75 70 65 0dbfs C6dbfs C12dbfs C18dbfs figure 14. inband sfdr vs. f out @ 2 msps (dc to clkin/2) a in C dbfs sfdr C dbc 85 35 C18 C16 0 C14 C12 C10 C6 C4 C2 C8 80 60 50 45 40 75 70 55 65 1.45mhz @ 16msps 363khz @ 4msps 727khz @ 8msps 2.9mhz @ 32msps figure 17. out-of-band single tone sfdr vs. a in @ f out = f clock /7 (dc to 3 1/2 clkin) a out C dbfs sfdr C dbc 85 35 C18 C16 0 C14 C12 C10 C6 C4 C2 C8 80 60 50 45 40 75 70 55 65 5.6/6.4mhz @ 16msps 1.4/1.6mhz @ 4msps 2.8/3.2mhz @ 8msps 11.2/12.8mhz @ 32msps figure 20. out-of-band two tone sfdr vs. a out @ f out = f clock /2.7 (dc to 3 1/2 clkin) f out C mhz sfdr C dbc 85 35 0 0.2 0.8 0.3 0.4 0.5 0.6 0.7 80 55 50 45 40 70 60 75 65 0dbfs C6dbfs C12dbfs C18dbfs figure 15. out-of-band sfdr vs. f out @ 2 msps (clkin/2 to 3 1/2 clkin) f clk C msps snr C db 80 75 60 10 20 30 70 65 dvdd = 3.3v dvdd = 5.0v figure 18. snr vs. f clkin @ f out = 2 mhz (dc to clkin/2) 10db C div C10 C80 C110 0 128.0 25.6 51.2 76.8 102.4 C20 C70 C90 C100 C50 C60 C30 C40 figure 21. multitone spectral plot @ 32 msps (dc to 4 clkin)
ad9774 C10C rev. b functional description figure 22 shows a simplified block diagram of the ad9774. the ad9774 is a complete, 4 oversampling, 14-bit dac that in- cludes two cascaded 2 interpolation filters, a phase-locked loop (pll) clock multiplier, and a 1.20 volt bandgap voltage refer- ence. the 14-bit dac provides two complementary current outputs whose full-scale current is determined by an external resistor. input data that is latched into the edge-triggered input latches is first interpolated by a factor of four by the interpolation filters before updating the 14-bit dac. a pll clock multiplier produces the necessary internally synchronized 1 , 2 and 4 clocks from an external reference. the ad9774 can support input data rates as high as 32 msps, corresponding to a dac update rate of 128 msps. the analog and digital sections of the ad9774 have separate power supply inputs (i.e., avdd and dvdd) that can operate over a 2.7 v to 5.5 v range. a separate supply input (i.e., pllvdd) having a similar operating range is also provided for the pll clock multiplier. to maintain optimum noise and dis- tortion performance, pllvdd should be maintained at the same voltage level as dvdd. vco in/ext pll divide pllcom pll clock multiplier refio snooze iouta fsadj ad9774 sleep dcom dvdd icomp acom avdd +1.2v reference and control amp pll enable plllock clk4 3 in pllvdd lpf ioutb edge triggered latches 14 14-bit dac data inputs (db13Cdb0) 2 3 2 3 1 3 2 3 4 3 4 3 14 14 14 clk in/out refcomp reflo figure 22. functional block diagram preceding the 14-bit dac are two cascaded 2 digital interpola- tion filter stages based on a 55- and 23-tap halfband symmetric fir topology. edge triggered latches are used to latch the input data on the rising edge of clk in/out. the composite fre- quency and impulse response of both filters are shown in fig- ures 2a and 2b. table i and table ii list the idealized filter coefficients for each of the filter stages. the interpolation filters essentially multiply the input data rate to the dac by a factor of four relative to its original input data rate while simultaneously reducing the magnitude of the images associated with the origi- nal input data rate. the benefits of an interpolation filter are clearly seen in figure 23, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to a digital interpolation filter. images of the sine wave signal appear around multiples of the dacs input data rate as predicted by sampling theory. these undesirable images will also appear at the output of a reconstruction dac, although modified by the dacs sin(x)/(x) roll-off response. in many bandlimited applications, these images must be sup- pressed by an analog filter following the dac. the complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. adding to the complexity of this analog filter may be the requirement of compensating for the dacs sin(x)/x response. referring to figure 23, the new first image associated with the dacs higher data rate after interpolation is pushed out fur- ther relative to the input signal. the old first image associated with the lower dac data rate before interpolation is suppressed by the digital filter. as a result, the transition band for the ana- log reconstruction filter is increased, thus reducing the complex- ity of the analog filter. furthermore, the sin(x)/x roll-off over the effective passband (i.e., dc to f clock /2) is significantly reduced. the ad9774 includes a pll clock multiplier that produces the necessary internally synchronized 1 , 2 and 4 clocks for the edge triggered latches, interpolation filters and dacs. the pll clock multiplier typically accepts an input data clock, clk in/out, as its reference source. alternatively, it can also be configured using an external 4 clock via clk4 in. the plldivide, vco in/ext, pllenable, and plllock are control inputs/outputs used in the pll clock generator. refer to the pll clock multiplier operation sec- tion for a detailed discussion on its operation. the digital section of the ad9774 also includes several other control inputs and outputs. the sleep and snooze inputs provide different power-saving modes as discussed in the sleep and snooze section. fundamental 4f clock 2f clock frequency domain 4f clock dacs "sinx" x 2f clock 1 4 f clock fundamental digital filter suppressed "old" 1 st image "new" 1st image 4f clock 2f clock 1 f clock time domain 4x interpolation filter input data latch dac 4 3 f clock f clock 4x 1 st image figure 23. time and frequency domain example of digital interpolation filter
ad9774 C11C rev. b pll clock multiplier operation the phase lock loop (pll) clock multiplier is intrinsic to the operation of the ad9774 in that it produces the necessary inter- nally synchronized 1 , 2 and 4 clocks for the edge triggered latches, interpolation filters and dacs. figure 24 shows a func- tional block diagram of the pll clock multiplier, which con- sists of a phase detector, a charge pump, a voltage controlled oscillator (vco), a divide-by-n circuit and some control inputs/ outputs. it produces the required internal clocks for the ad9774 by using one of two possible externally applied reference clock sources applied to either clkin or clk4 in. pllenable and vco in/ext are active high control inputs used to enable the charge pump and vco respectively. to maintain optimum noise and distortion performance, pllvdd and dvdd should be set to similar voltage levels. if a separate supply cannot be provided for pllvdd, pllvdd can be tied to dvdd using an lc filter network similar to that shown in figure 41. many applications will select a reference clock operating at the data input rate as shown in figure 24. in this case, the external clock source is applied to clkin and the pll clock multiplier is fully enabled by tying pllenable and vco in/ext to pllvdd. note, clkin must adhere to the timing require- ments shown in figure 1. a 1.5 k w resistor and 0.01 m f ceramic capacitor connected in series from lpf to pllvdd are re- quired to optimize the phase noise vs. settling/acquisition time characteristics of the pll. plllock is a control output, ac- tive high, which may be monitored upon system power-up to indicate that the pll is successfully locked to clkin. note, applications employing multiple ad9774 devices will benefit from the pll clock multipliers ability to ensure precise simul- taneous updating/phase synchronization of these devices when driven by the same input clock source. plldivide is used to preset the lock-in range of the pll. it should be tied to pllcom if clkin is greater than 10 mhz and to pllvdd if clkin is between 5.5 mhz and 10 mhz. for operation below 5.5 mhz (i.e., input data rates less than 5.5 msps), the internal charge pump and vco should be disabled by tying pllenable and vco in/ext low. in this case, the user must supply a system clock operating at 4 the input data rate as discussed below. connect to pllcom connect to pllvdd pll divide clk in/out plllock pll enable lpf 1.5k v 0.01 m f +2.7 to +5.5 v d +2.7 to +5.5 v d pll vdd pll com vco vco in/ext dvdd clk 4 3 in dcom divide- by-n 4 8 4 4 4 2 4 1 vco charge pump phase detector ad9774 figure 24. clock multiplier with pll enabled there are two cases in which a user may consider or be required to disable the internal pll clock multiplier and supply the ad9774 with an external 4 system clock. applications already containing a system clock operating at four (i.e., 4 ) the input data rate may consider using it as the master clock source. ap- plications with input data rates less than 5.5 msps must use a master 4 clock. in any of these cases, the clock source is applied to clk4 in and the pll is partially disabled by typing pllenable and vco in/ext to pllcom as shown in figure 25. lpf may remain open since this portion of the pll circuitry is disabled. the divide-by-n circuit still remains enabled providing a 1 or 2 internal clock at clock in/out depending on the state of plldivide. since the digital input data is latched into the ad9774 on the rising edge of the 1 clock, plldivide should be tied to pllcom such that the 1 clock appears as an output at clock in/out. the input data should be stable 5 ns (i.e., data set-up) before the rising edge of the 1 clock appearing at clock in/out and remain stable for 1 ns after the rising edge (i.e., data hold) to ensure proper latching. note, the rising edge of the 1 clock occurs approximately 9 ns to 15 ns relative to the falling edge of the clk4 input. if a data timing issue exists between the ad9774 and its external driver device, the clk4 input can be inverted via an external gate to ensure proper set-up and hold time. pll divide plllock pll enable lpf +2.7 to +5.5 v d pll vdd pll com vco vco in/ext dvdd clk 4 3 in dcom divide- by-n 4 8 4 4 4 2 4 1 vco charge pump phase detector ad9774 clk in/out +2.7 to +5.5 v d figure 25. clock divider with pll disabled dac operation the 14-bit dac along with the 1.2 v reference and reference control amplifier is shown in figure 26. the dac consists of a large pmos current source array capable of providing up to 20 ma of full-scale current, i outfs . the array is divided into 31 equal currents which make up the five most significant bits (msbs). the next four bits or middle bits consist of 15 equal current sources whose values are 1/16th of an msb current source. the remaining lsbs are binary weighted fractions of the middle-bits current sources. all of these current sources are switched to one or the other of two output nodes (i.e., iouta or ioutb) via pmos differential current switches. implement- ing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dacs high output impedance (i.e., > 100 k w ).
ad9774 C12C rev. b +2.7 to +5.5v a 1.20v ref reflo avdd acom icomp 0.1 m f lsb switches segmented switches 1.91k v iouta ioutb current source array refio fs adj 0.1 m f 50pf ad9774 refcomp 0.1 m f figure 26. block diagram of internal dac, 1.2 v reference, and reference control circuits the full-scale output current is regulated by the reference con- trol amplifier and can be set from 2 ma to 20 ma via an exter- nal resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage reference, refio, sets the reference current, i ref , which is mirrored over to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is exactly thirty-two times the value of i ref . dac transfer function the ad9774 provides complementary current outputs, iouta and ioutb. iouta will provide a near full-scale current out- put, i outfs , when all bits are high (i.e., dac code = 16383) while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb is a func- tion of both the input code and i outfs and can be expressed as: iouta = ( dac code /16384) i outfs (1) ioutb = (16383 C dac code )/16384 i outfs (2) where dac code = 0 to 16383 (i.e., decimal representation). as previously mentioned, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load may represent the equivalent load resistance seen by iouta or ioutb as would be the case in a doubly terminated 50 w or 75 w cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply: v outa = iouta r load (5) v outb = ioutb r load (6) note that the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain speci- fied distortion and linearity performance. the differential voltage, v diff , appearing across iouta and ioutb is: v diff = ( iouta C ioutb ) r load (7) substituting the values of iouta, ioutb and i ref ; v diff can be expressed as: v diff = {(2 dac code C 16383)/16384} v diff = { (32 r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the ad9774 differentially. first, the differential operation will help cancel common-mode error sources associ- ated with iouta and ioutb such as noise, distortion and dc offsets. second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (vouta and voutb) or differential output (v diff ) of the ad9774 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relation- ship as shown in equation 8. reference operation the ad9774 contains an internal 1.20 v bandgap reference that can be easily disabled and overridden by an external reference. refio serves as either an input or output, depending on whether the internal or external reference is selected. if reflo is tied to acom, as shown in figure 27, the internal reference is activated, and refio provides a 1.20 v output. in this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 m f or greater from refio to reflo. if any additional loading is required, refio should be buffered with an external amplifier having an input bias cur- rent less than 100 na. 50pf +1.2v ref avdd reflo current source array +2.7 to +5.5v a refio fsadj 2k v 0.1 m f ad9774 additional load optional external ref buffer 0.1 m f refcomp figure 27. internal reference configuration the internal reference can be disabled by connecting reflo to avdd. in this case, an external reference may then be applied to refio as shown in figure 28. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 m f compensation capacitor is not required since the internal reference is disabled, and the high input im- pedance (i.e., 1 m w ) of refio minimizes any loading of the external reference.
ad9774 C13C rev. b 50pf +1.2v ref avdd reflo current source array +2.7 to +5.5v a refio fs adj r set ad9774 external ref i ref = v refio /r set avdd reference control amplifier v refio 0.1 m f refcomp figure 28. external reference configuration reference control amplifier the ad9774 also contains an internal control amplifier that is used to regulate the dacs full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in figure 28, such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied over to the segmented current sources with the proper scaling factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 m a and 625 m a. the wide adjustment span of i outfs provides several application benefits. the first benefit relates directly to the power dissipation of the ad9774, which is pro- portional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. there are two methods by which i ref can be varied for a fixed r set . the first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of refio is varied over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply amplifier or dac, thus allowing i ref to be varied for a fixed r set . since the input impedance of refio is approximately 1 m w , a simple, low cost r-2r ladder dac configured in the voltage mode topology may be used to control the gain. this circuit is shown in figure 30 using the ad7524 and an external 1.2 v reference, the ad1580. the second method may be used in a dual-supply system in which the common-mode voltage of refio is fixed, and i ref is varied by an external voltage, v gc , applied to r set via an ampli- fier. an example of this method is shown in figure 29 in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 v. the external voltage, v gc , is referenced to acom and should not exceed 1.2 v. the value of r set is such that i refmax and i refmin do not exceed 62.5 m a and 625 m a, respectively. the associated equations in figure 29 can be used to determine the value of r set . 50pf +1.2v ref avdd reflo current source array +2.7 to +5.5v a refio fsadj r set ad9774 i ref v gc 1 m f i ref = (1.2Cv gc )/r set with v gc , v refio and 62.5 m a # i ref # 625a 0.1 m f refcomp figure 29. dual supply gain control circuit analog outputs the ad9774 produces two complementary current outputs, iouta and ioutb, which may be configured for single-end or differential operation. iouta and ioutb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb , can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. figure 31 shows the equivalent analog output circuit of the ad9774 consisting of a parallel combination of pmos differen- tial current switches associated with each segmented current source. the output impedance of iouta and ioutb is deter- mined by the equivalent parallel combination of the pmos switches and is typically 100 k w in parallel with 5 pf. due to the nature of a pmos device, the output impedance is also slightly depe ndent on the output voltage (i.e., v outa and v outb ) and, to a lesser extent, the analog supply voltage, avdd, and full-scale current, i outfs . although the output impedances signal dependency can be a source of dc nonlinearity and ac linear- ity (i.e., distortion), its effects can be limited if certain precau- tions are noted. 1.2v 50pf +1.2v ref avdd reflo current source array +2.7 to +5.5v a refio fsadj r set ad9774 i ref = v ref /r set avdd v ref v dd r fb out1 out2 agnd db7Cdb0 ad7524 ad1580 0.1v to 1.2v 0.1 m f refcomp figure 30. single supply gain control circuit
ad9774 C14C rev. b ad9774 avdd iouta ioutb r load r load figure 31. equivalent analog output circuit iouta and ioutb also have a negative and positive voltage compliance range. the negative output compliance range of C1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the ad 9774. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. operation beyond the positive compli ance range will induce clipping of the output signal, which severely degrades the ad9774s linearity and distortion performance. for applications requiring the optimum dc linearity, iouta and/or ioutb should be maintained at a virtual ground via an i-v op amp configuration. maintaining iouta and/or ioutb at a virtual ground keeps the output impedance of the ad9774 fixed, signifi cantly reducing its effect on linearity. however, it does not necessarily lead to the optimum distortion perfor- mance due to limitations of the i-v op amp. note that the inl/dnl specifications for the ad9774 are measured in this manner using iouta. in addition, these dc linearity specifi- cations remain virtually unaffected over the specified power supply range of 2.7 v to 5.5 v. operating the ad9774 with reduced voltage output swings at iouta and ioutb in a differential or single-ended output configuration reduces the signal dependency of its output im- pedance thus enhancing distortion performance. although the voltage compliance range of iouta and ioutb extends from C1.0 v to +1.25 v, optimum distortion performance is achieved when the maximum full-scale signal at iouta and ioutb does not exceed approximately 0.5 v. a properly selected trans- former with a grounded center-tap will allow the ad9774 to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at iouta and ioutb. dc-coupled applications requiring a differential or single-ended output configuration should size r load accord- ingly. refer to applying the ad9774 section for examples of various output configurations. the most significant improvement in the ad9774s distortion and noise performance is realized using a differential output configuration. the common-mode error sources of both iouta and ioutb can be substantially reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the recons tructed waveforms frequency content increases and/or its amplitude decreases. the distortion and noise performance of the ad9774 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, i outfs . operating the analog supply at 5.0 v ensures maximum headroom for its internal pmos current sources and differential switches leading to improved distortion performance. alth ough i outfs can be set between 2 ma and 20 ma, selecting an i outfs of 20 ma will provide the best dis- tortion and noise performance. the noise performance of the ad9774 is affected by the digital supply (dvdd), output fre- quency, and increases with increasing clock rate. operating the ad9774 with low voltage logic levels between 3 v and 3.3 v will slightly reduce the amount of on-chip digital noise. in summary, the ad9774 achieves the optimum distortion and noise performance under the following conditions: (1) differential operation. (2) positive voltage swing at iouta and ioutb limited to +0.5 v. (3) ioutfs set to 20 ma. (4) analog supply (avdd) set at 5.0 v. (5) digital supply (dvdd) and phase lock loop supply (pllvdd) set at 3.0 v to 3.3 v with appropriate logic levels. note that the ac performance of the ad9774 is characterized under the above-mentioned operating conditions. digital inputs/outputs the digital input of the ad9774 consists of 14 data input pins and a clock input pin, and several control input pins. since some of the internal logic is operated from dvdd and pllvdd, they must be set to the same or similar levels to ensure proper compatibility with any external logic/drivers. the two digital outputs of the ad9774, pll lock and clk out originate from the internal pll circuitry and thus its output logic levels will be set by pllvdd. the 14-bit parallel data inputs follow standard positive binary coding where db13 is the most significant bit (msb), and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb pro- duces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch and is designed to support a clock and input data rate as high as 32 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth as shown in figure 1. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met. the digital inputs are cmos-compatible with logic thresholds, v threshold, set to approximately half the digital positive supply (i.e., dvdd or pllvdd) or v threshold = dvdd /2 ( 20%) the internal digital circuitry of the ad9774 is capable of oper ating over a digital supply range of 2.7 v to 5.5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh(max) . a dvdd of 3 v to 3.3 v will typically ensure proper compatibility with most ttl logic families. figure 32 shows the equivalent digital input circuit for the data and clock inputs.
ad9774 C15C rev. b dvdd digital input figure 32. equivalent digital input since the ad9774 is capable of being updated up to 32 msps, the quality of the clock and data input signals are important in achieving the optimum performance. operating the ad9774 with reduced logic swings and a corresponding digital supply (dvdd) will result in the lowest data feedthrough and on-chip digital noise. the drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the ad9774 as well as its required min/max input logic level thresholds. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 w to 100 w ) between the ad9774 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. the external clock driver circuitry should provide the ad9774 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a recon- structed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application. sleep and snooze mode operation the ad9774 has a sleep function that turns off the output current and reduces the supply current to less than 5 ma over the specified supply range of 2.7 v to 5.5 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the ad9774 takes less than 0.1 m s to power down and approximately 6.4 m s to power back up. the snooze mode should be considered as an alternative power-savings option if the power-up characteristics of the sleep mode are unsuitable. this mode, which is also activated by applying a logic level 1 to the snooze pin, disables the ad9774s digital filters only, resulting in significant power savings. both the sleep and snooze pins should be tied to dcom if power savings is not required. power dissipation the power dissipation, p d , of the ad9774 is dependent on several factors, including: (1) avdd, pllvdd, and dvdd, the power supply voltages; (2) i outfs , the full-scale current output; (3) f clock , the update rate; and (4) the reconstructed digital input waveform. the power dissipation is directly pro- portional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs, as shown in figure 33, and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input wave- form, f clock , and digital supply dvdd. figures 34 and 35 show i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively. note, how i dvdd is reduced by more than a factor of 2 when dvdd is reduced from 5 v to 3 v. i outfs C ma 30 0 220 4 6 8 1012141618 25 20 15 10 5 i avdd C ma figure 33. i avdd vs. i outfs ratio C f out / f clock 200 180 20 0.01 1.0 0.10 i dvdd C ma 100 80 60 40 140 120 160 0 32msps 16msps 8msps 4msps figure 34. i dvdd vs. ratio @ dvdd = 5 v ratio C f out / f clock 100 0 0.01 1.0 0.10 i dvdd C ma 90 50 80 70 60 40 30 20 10 32msps 16msps 8msps 4msps figure 35. i dvdd vs. ratio @ dvdd = 3 v for those applications requiring the ad9774 to operate under the following conditions: (1) avdd, pllvdd and dvdd = +5 v; (2) f clock > 25 msps; and (3) ambient temperatures > 70 c; proper thermal management via a heatsink or thermal epoxy is recommended.
ad9774 C16C rev. b applying the ad9774 output configurations the following sections illustrate some typical output configura- tions for the ad9774. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the opti- mum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if iouta and/or ioutb is connected to an approximately sized load resistor, r load , referred to acom. this configura- tion may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus convert- ing iouta or ioutb into a negative unipolar voltage. this configuration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion as shown in figure 36. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformers passband. an rf transformer such as the mini-circuits t1-1t provides excellent rejec tion of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load ad9774 22 21 mini-circuits t1-1t optional r diff iouta ioutb figure 36. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the ad9774. a differential resistor, r diff , may be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is deter- mined by the transformers impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential using an op amp an op amp can also be used to perform a differential-to-single- ended conversion as shown in figure 37. the ad9774 is config ured with two equal load resistors, r load , of 25 w . the differential voltage developed across iouta and ioutb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across iouta and ioutb, forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distor- tion performance by preventing the dacs high slewing output from overloading the op amps input. ad9774 22 iouta ioutb 21 c opt 500 v 225 v 225 v 500 v 25 v 25 v ad8055 figure 37. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit using the ad8055 is configured to provide some additional signal gain. the op amp must operate from a dual supply since its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential perform- ance of the ad9774 while meeting other system level objectives (i.e., cost, power) should be selected. the op amps differential gain, its gain setting resistor values and full-scale output swing capabilities should all be considered when optimizing this circuit. the differential circuit shown in figure 38 provides the neces- sary level-shifting required in a single supply system. in this case, avdd, which is the positive analog supply for both the ad9774 and the op amp, is also used to level-shift the differential output of the ad9774 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. ad9774 22 iouta ioutb 21 c opt 500 225 225 1k 25 25 ad8041 1k avdd figure 38. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 39 shows the ad9774 configured to provide a unipolar output range of approximately 0 v to +0.5 v for a doubly termi- nated 50 w cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 w . in this case, r load represents the equivalent load resistance seen by iouta. the unused output (ioutb) can be connected to acom di- rectly. different values of i outfs and r load can be selected as
ad9774 C17C rev. b long as the positive compliance range is adhered to. one addi- tional consideration in this mode is the integral nonlinearity (inl) as discussed in the analog output section of this data sheet. for optimum inl performance, the single-ended, buff- ered voltage output configuration is suggested. ad9774 iouta ioutb 21 50 v 50 v v outa = 0 to +0.5v i outfs = 20ma 22 figure 39. 0 v to +0.5 v unbuffered voltage output single-ended buffered voltage output configuration figure 40 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the ad9774 output current. u1 maintains iouta (or ioutb) at a virtual ground, thus minimizing the nonlinear output impedance effect on the dacs inl performance as discussed in the analog output section. although this single-ended configuration typi- cally provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by u1s slewing capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced. ad9774 22 iouta ioutb 21 c opt 200 v u1 v out = i outfs 3 r fb i outfs = 10ma r fb 200 v figure 40. unipolar buffered voltage output power and grounding considerations in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection, placement and routing and supply bypassing and grounding. figures 44C49 illustrate the recommended printed circuit board ground, power and signal plane layouts that are implemented on the ad9774 evaluation board. proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9774 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physi- cally possible. similarly, dvdd, the digital supply, should be decoupled to dcom and pllvdd, the phase lock loop supply, should be decoupled to pllcom. for those applications requiring a single +5 v or +3 v supply for both the analog, digital supply and phase lock loop supply, a clean avdd and/or pllvdd may be generated using the circuit shown in figure 41. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr type electrolytic and tanta- lum capacitors. 100 m f elect. 10-22 m f tant. 0.1 m f cer. +5v or +3v power supply ferrite beads avdd acom ttl/cmos logic circuits figure 41. differential lc filter for single +5 v or +3 v applications maintaining low noise on power supplies and ground is critical to obtain optimum results from the ad9774. if properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding current trans- port, etc. in mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. all analog ground pins of the dac, reference and other analog components should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the dac to maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac as well as any clock signals. on the analog side, this includes the dac output signal, reference signal and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous volt- age drops in the signal ground paths. it is recommended that all connections be short, direct and as physically close to the pack- age as possible in order to minimize the sharing of conduction paths between different currents. when runs exceed an inch in length, strip line techniques with proper termination resistors should be considered. the necessity and value of this resistor will be dependent upon the logic family used. for a more detailed discussion of the implementation and con- struction of high speed, mixed signal printed circuit boards, refer to analog devices application notes an-280 and an-333.
ad9774 C18C rev. b multitone performance considerations and characterization the frequency domain performance of high speed dacs has traditionally been characterized by analyzing the spectral output of a reconstructed full-scale (i.e., 0 dbfs), single-tone sine wave at a particular output frequency and update rate. although this characterization data is useful, it is often insufficient to reflect a dacs performance for a reconstructed multitone or spread- spectrum waveform. in fact, evaluating a dacs spectral performance using a f ull-scale, single tone at the highest specified frequency (i.e., f h ) of a bandlimited waveform is typically indicative of a dacs worst-case performance for that given waveform. in the time domain, this full-scale sine wave repre- sents the lowest peak-to-rms ratio or crest factor (i .e., v peak / v rms) that this bandlimited signal will encounter. 10db C div C100 C60 C90 0 16 4812 0 C50 C70 C80 C30 C40 C10 C20 14 2610 figure 42a. multitone spectral plot time 1.0000 0.8000 C1.0000 volts C0.2000 C0.4000 C0.6000 C0.8000 0.2000 0.0000 0.4000 0.6000 figure 42b. time domain snapshot of the multitone waveform however, the inherent nature of a multitone, spread spectrum, or qam waveform, in which the spectral energy of the wave- form is spread over a designated bandwidth, will result in a higher peak-to-rms ratio when compared to the case of a simple sine wave. as the reconstructed waveforms peak-to-average ratio increases, an increasing amount of the signal energy is concentrated around the dacs midscale value. figure 42a is just one example of a bandlimited multitone vector (i.e., eight tones) ce ntered around one-half the nyquist bandwidth (i.e., f clock /4). t his particular multitone vector, has a peak-to-rms ratio of 13.5 db com pared to a sine waves peak-to-rms ratio of 3 db. a snapshot of this reconstructed multitone vector in the time domain as shown in figure 43b reveals the higher signal content around the midscale value. as a result, a dacs small- scale dynamic and static linearity becomes increasingly critical in obtaining low intermodulation distortion and maintaining sufficient carrier-to-noise ratios for a given modulation scheme. a dacs small-scale linearity performance is also an important consideration in applications where additive dynamic range is required for gain control purposes or predistortion signal conditioning. for instance, a dac with sufficient dynamic range can be used to provide additional gain control of its reconstructed signal. in fact, the gain can be controlled in 6 db increments by simply performing a shift left or right on the dacs digital input word. other applications may intentionally predistort a dacs digital input signal to compensate for nonlinearities associated with the s ubsequent analog compo- nents in the signal chain. for example, the signal compression associated with a power amplifier can be compensated for by predisto rting the dacs digital input with the inverse nonlinear transfer function of the power amplifier. in either case, the dacs performance at reduced signal levels should be carefully evaluated. a full-scale single tone will induce all of the dynamic and static nonlinearities present in a dac that contribute to its distortion and hence sfdr performance. as the frequency of this recon- structed full-scale, single-tone waveform increases, the dynamic nonlinearities of any dac (i.e., ad9774) tend to dominate thus contributing to the roll-off in its sfdr per formance. however, unlike most dacs, which employ an r-2r ladder for the lower bit current segmentation, the ad9774 (as well as other txdac members) exhibits an improvement in distortion performance as the amplitude of a single tone is reduced from its full-scale level. this improvement in distortion performance at reduced signal levels is evident if one compares the sfdr performance vs. frequency at different amplitudes (i.e., 0 dbfs, C6 dbfs and C12 dbfs) and sample rates as shown in figures 4 through 15. maintaining decent small-scale linearity across the full span of a dac transfer function is also critical in maintaining excellent multitone performance. although characterizing a dacs multitone performance tends to be application-specific, much insight into the potential per- formance of a dac can also be gained by evaluating the dacs swept power (i.e., amplitude) performance for single, dual and multitone test vectors at different clock rates and carrier frequen- cies. the dac is evaluated at different clock rates when recon- structing a specific waveform whose amplitude is decreased in 3 db increments from full-scale (i.e., 0 dbfs). for each specific waveform, a graph showing the sfdr (over nyquist) perfor- mance vs. amplitude can be generated at the different tested clock rates as shown in figures 19 and 20. note that the carrier(s)-to-clock ratio remains constant in each figure.
ad9774 C19C rev. b a multitone test vector may consist of several equal amplitude, spaced carriers each representative of a channel within a defined bandwidth as shown in figure 42a. in many cases, one or more tones are removed so the intermodulation distortion performance of the dac can be evaluated. nonlinearities associated with the dac will create spurious tones of which some may fall back into the empty channel thus limiting a channels carrier-to-noise ratio. other spurious components falling outside the band of interest may also be important, depending on the systems spectral mask and filtering requirements. this particular test vector was centered around one-half the nyquist bandwidth (i.e., f clock /4) with a passband of f clock /16. centering the tones at a much lower region (i.e., f clock /10) would lead to an improvement in performance while centering the tones at a higher region (i.e., f clock /2.5) would result in a degradation in performance. figure 43a shows the sfdr vs. amplitude at 32 msps up to the nyquist frequency while fig- ure 43b shows the sfdr vs. amplitude within the passband of the test vector. in assessing a dacs multitone performance, it is also recommended that several units be tested u nder exactly the same conditions to determine any performance variability. ad9774 evaluation board general description the ad9774-eb is an evaluation board for the ad9774 14-bit dac converter. careful attention to layout and circuit design, combined with a prototyping area, allows the user to easily and effectively evaluate the ad9774 in signal reconstruction applica- tions, where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad9774 in various configurations. the digital inputs are designed to be driven directly from various word generators with the onboard option to add a resistor network for proper load termination. provisions are also made to operate the ad9774 with either the internal or external reference or to exercise the sleep or snooze power-savings feature. a out C dbfs 80 40 C18 0 C16 C14 C12 C10 C8 C6 C4 C2 75 70 65 60 55 sfdr C dbc 50 45 figure 43a. multitone sfdr vs. a out @ 32 msps (up to nyquist) a out C dbfs 80 50 C18 0 C16 C14 C12 C10 C8 C6 C4 C2 75 70 65 60 sfdr C dbc 55 8msps 16msps 32msps figure 43b. multitone sfdr vs. a out @ 32 msps (within multitone passband)
ad9774 C20C rev. b db13 pllvdd avdd j2 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 top view (not to scale) ad9774 12 13 14 15 16 17 18 19 20 21 22 fsadj refio reflo unused pllenable pllcom u2,u4 33 db12 db11 db10 db9 db8 nc = no connect db7 db6 db5 db4 pllvdd dgnd plllock lpf dvdd vco in/ext plldivide dcom snooze dcom iouta ioutb avdd acom dgnd db3 db2 db1 db0 nc nc nc clk4 3 in icomp clk in/out sleep x9 1 2 3 6 5 4 agnd tp tp tp tp pllgnd tp tp tp p dgnd tp tp tp tp p pllgnd p p r1 1.91k v c4 20pf r2 50 v r3 50 v r10 100 v tp16 tp17 c2 10 m f avdd agnd dgnd dvdd c3 10 m f tp14 tp15 c1 0.1 m f 50 v 50 v tp tp c13 0.1 m f c12 0.1 m f tp idiff c7 0.1 m f s3 c10 0.1 m f p c8 0.01 m f tp r5 1.5k v s2 s1 tp19 pllvdd tp18 ib ia tp u7 u3 edge_40 r4 50 v tp13 j1 j8 dgnd dvdd c11 0.1 m f ext clk 1 u8 u6 40 c9 10 m f c5 20pf j4 33 refcomp c6 0.1 m f dcom figure 44. evaluation board schematic
ad9774 C21C rev. b figure 45. silkscreen layertop figure 46. component side pcb layout (layer 1)
ad9774 C22C rev. b figure 47. ground plane pcb layout (layer 2) figure 48. power plane pcb layout (layer 3)
ad9774 C23C rev. b figure 49. solder side pcb layout (layer 4) figure 50. silkscreen layerbottom
ad9774 C24C rev. b outline dimensions dimensions shown in millimeters and (inches). c3198bC0C11/98 printed in u.s.a. 44-lead metric quad flatpack (s-44) top view (pins down) 12 44 1 11 22 23 34 33 0.45 (0.018) 0.30 (0.012) 13.45 (0.529) 12.95 (0.510) 8.45 (0.333) 8.30 (0.327) 10.10 (0.398) 9.90 (0.390) 0.80 (0.031) bsc 2.10 (0.083) 1.95 (0.077) 0.23 (0.009) 0.13 (0.005) 0.25 (0.01) min seating plane 0 min 2.45 (0.096) max 1.03 (0.041) 0.73 (0.029)

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